Electronic Design Automation¶
Graph-Based RTL Generation¶
Challenge: Translating abstract graph-based models (like data flow graphs or process communication graphs) directly into structurally correct RTL code.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2013 | DAC | Columbia | A Method to Abstract RTL IP Blocks into C++ Code and Enable High-Level Synthesis | process communication graph; I/O port loop unrolling; HLS design space expansion | |||
| 2024 | ISEDA | UESTC | GraphRTL: an Agile Design Framework of RTL Code from Data Flow Graphs | graph error detection kernel; DFS based graph equivalent reconstruction; template/Scala based DFG and CFG merging |
Dynamically Scheduled HLS and Dataflow Circuits¶
Challenge: HLS-generated dataflow circuits force successive instances of the same operation to execute strictly in program order due to the absence of token tags, preventing exploitation of parallelism analogous to out-of-order superscalar processors—particularly harmful when long-latency operations or high-II inner loops create pipeline bubbles.
Solution: Introduce selective token tagging and alignment components (TAGGER, ALIGNER, UNTAGGER) into untagged dataflow circuits at formally derived minimal positions, enabling out-of-order execution of targeted operations while preserving correctness for loop-carried dependencies and memory hazards.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2024 | FPGA | EPFL | Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits | TAGGER/ALIGNER/UNTAGGER components for selective token tagging in untagged dataflow circuits; dirty-node and unaligned-edge sets for minimal ALIGNER positioning; noncyclic/cyclic control-flow clustering to prevent alignment count mismatch | 5 | 4 | 4 |
Spatial Accelerator Generation¶
Challenge: Building parameterized compilation frameworks to rapidly synthesize, evaluate, and deploy diverse spatial architectures (e.g., systolic arrays) while decoupling algorithm mapping from hardware generation.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2020 | ISCA | UCLA | DSAGEN: Synthesizing Programmable Spatial Accelerators | architecture description graph (ADG); solution-repairing spatial scheduler to avoid redundant re-compilation; composable decoupled spatial primitives for approximating diverse accelerators | 4 | 3 | 4 |
| 2021 | ASPLOS | Cornell | A compiler infrastructure for accelerator generators | a split representation combining a high-level control flow language with a hardware-like structural language; pass-based compiler; systolic array generator; live-range-based register-sharing | 4 | 3 | 3 |
| 2021 | DAC | UCB | Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration | exploring diverse systolic array dimensions and dataflows; RoCC(Rocket Custom Coprocessor) integration with unified virtual memory support; FPGA-accelerated full-system simulation | 4 | 5 | 4 |
LLM-Driven RTL Generation¶
Challenge: Overcoming the lack of domain knowledge and strict syntax adherence in generic Large Language Models (LLMs) to generate functionally correct and synthesizable Verilog code.
Agentic RTL Code Generation¶
Challenge: Single-shot LLM prompting loses circuit details and lacks domain-specific feedback loops for correcting syntax and functional RTL errors.
Solution: Equip RTL coding agents with task decomposition, simulator feedback, graph-based circuit context retrieval, and waveform-aware debugging tools.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2024 | arXiv | UCSD | MAGE: A Multi-Agent Engine for Automated RTL Code Generation | multi-agent; high-temperature sampling and ranking; verilog-state checkpoint debugging | |||
| 2025 | AAAI | NVIDIA | VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool | Task and Circuit Relation Graph; AST-based waveform tracing tool; task-driven circuit relation graph retrieval agent; code agent and debug agent split; VerilogEval-Human v2 single-run flow | 4 | 3 | 4 |
RTL Model Training and Repair Data¶
Challenge: Verilog code models are bottlenecked by low-quality synthetic training data, non-textual RTL specifications, and small but recurring functional mistakes.
Solution: Curate Verilog-specific training data with code augmentation, self-reflection, correct-by-construction non-textual examples, and targeted code repair cases.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2024 | ICCAD | PKU | OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection | self-reflection mechanism; dataset augmentation methodology; VerilogFixEval benchmark | 2 | 4 | 2 |
| 2025 | ICLR | NVIDIA | CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair | correct-by-construction KMap/FSM/waveform data; VerilogEval-NonText subset; checkpoint error report construction; targeted code repair injection; SDG-CC-Repair training mixture | 4 | 3 | 3 |
Higher-Level RTL Code Generation¶
Challenge: raise the level of abstraction to specifically target the construction of applications
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2022 | PLDI | Cornell University | PDL: A High-Level Hardware Design Language for Pipelined Processors | one-instruction-at-a-time semantics; hardware description language; hazard locks; speculation API; guaranteed-correct pipelining | 3 | 3 | 3 |
| 2025 | ISCA | KAUST | Assassyn: A Unified Abstraction for Architectural Simulation and Implementation | unified simulation and RTL generation; asynchronous event-driven pipeline abstraction; function-as-stage programming model; transposed trace-waveform alignment | 3 | 3 | 3 |
RTL Code Generation Benchmarks¶
Challenge: The lack of standardized benchmarks for evaluating RTL code generation tools.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2023 | DATE | NYU | Benchmarking Large Language Models for Automated Verilog RTL Code Generation | verilog code training corpus; multi-level verilog coding problems for analysis | |||
| 2025 | arXiv | NVIDIA | Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification | CVDP benchmark; 783 human-authored Verilog problems; Agentic and Non-Agentic JSONL formats; Dockerized EDA tool harness; category-level failure clustering | 4 | 3 | 3 |
LLM-Driven Hardware Design Agents¶
Challenge: General-purpose LLM agents do not directly handle hardware design workflows that require domain knowledge, EDA tools, timing reports, layout checks, and task-specific collaboration patterns.
Solution: Use configurable graph-based task solving with single-AI, multi-AI, and multi-modality agents connected to hardware-specific tools, memory, and knowledge databases.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2025 | VLSI | NVIDIA | Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design | dynamic and static configurable task graph; sub-task node agent configuration; MCMM timing analysis agent; DRC Coder multi-modality agent; timing path debug static task graph | 3 | 3 | 2 |
Physical Design¶
Challenge: Optimizing the physical layout (placement and routing) of circuits on chips to meet timing, power, and area constraints, especially for large-scale heterogeneous architectures.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2019 | ICCAD | UT Austin | elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs | electrostatics-based placement for heterogeneous FPGAs; augmented Lagrangian formulation; preconditioning technique; normalized subgradient multiplier updating; unified instance area adjustment | 4 | 4 | 4 |
| 2023 | ICCAD | TAMU | Systolic Array Placement on FPGAs | Region-wise Sweep in Alternating Direction (R-SAD); partition enumeration and pruning; regularity-driven placement; DSP column placement optimization | 3 | 4 | 3 |
HLS-aware Physical Design¶
Challenge: Long compilation time for HLS designs due to the inherently sequential and complex physical implementation (place & route) flow.
Solution: Leverage HLS dataflow properties to enable a parallel physical implementation flow.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2022 | FPGA | UCLA | RapidStream: Parallel Physical Implementation of FPGA HLS Designs | split compilation; HLS-physical co-design; anchor registers; timing isolation; parallel placement and routing; stitching | 4 | 4 | 4 |
Logic Synthesis & Technology Mapping¶
Challenge: Mapping behavioral or structural RTL descriptions to complex, architecture-specific FPGA or ASIC primitives (like DSPs) efficiently and correctly, avoiding heuristic fallbacks.
Solution: Employ automated reasoning, such as sketch-guided program synthesis, to systematically explore the logic configuration space.
FPGA Technology Mapping¶
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2024 | ASPLOS | UW | FPGA Technology Mapping Using Sketch-Guided Program Synthesis | Lakeroad program synthesis-based technology mapper; architecture-independent sketch templates; automated semantics extraction from vendor HDL models; Rosette-based SMT solver translation | 3 | 4 | 3 |